Abstract: This paper proposes a design method of FPGA embedded logic analyzer for large storage in which the sample signals can be reselected.In this method,the JTAG hard core can be reused by constraining the placement and routing,and the sample signals can be reselected by changing the configurable registers via JTAG hard core.According to the measurement results,compared with the commercial tools,the demand of the embedded RAM resource can be reduced to the amount of 1/N which N equals the number of the sample groups,and the timing stability can be kept in observing the different signals.