Abstract: This article is implements a configurable FFT (Fast Fourier Transformation) hardware accelerators cycle accurate model based on SystemC.The mixed-Radix8 FFT,4parallel computation and memory architecture-based design are used in this model.The model can calculate 16-4m point single-precision floating-point complex FFT,the signal-to-noise ratio at the same time stable at more than 130 db.Compared with the model of same type,It can achieve an exact match with the hardware cycle,and guarantee much faster speed than hardware simulation,which achieves the effect of cooperating with hardware design and verification.