Abstract: The successive cancellation list (SCL) algorithm can improve the decoding performance of polar codes with short and moderate code lengths. However the recursive structure results in the lower throughput, large hardware complexity and cost. A LLR-SCL arithmetic based non-recursive structure is proposed. And a LLR-SCL decoder of length 1 024 and list size L=2 is designed. The simulation result shows the error performance is good. Also, the proposed LLR-SCL decoder is implemented under Xillinx XC7V2000 FPGA. The synthesis result shows that the utilization rate of hardware resources is low and the frequency is up to 227 MHz.