柳沐璇, 张树丹, 唐彩彬. 一种基于AHB总线的DESIP核设计[J]. 微电子学与计算机, 2014, 31(10): 69-71.
引用本文: 柳沐璇, 张树丹, 唐彩彬. 一种基于AHB总线的DESIP核设计[J]. 微电子学与计算机, 2014, 31(10): 69-71.
LIU Mu-xuan, ZHANG Shu-dan, TANG Cai-bin. A Design of DES IP Core Based on AHB Bus[J]. Microelectronics & Computer, 2014, 31(10): 69-71.
Citation: LIU Mu-xuan, ZHANG Shu-dan, TANG Cai-bin. A Design of DES IP Core Based on AHB Bus[J]. Microelectronics & Computer, 2014, 31(10): 69-71.

一种基于AHB总线的DESIP核设计

A Design of DES IP Core Based on AHB Bus

  • 摘要: 设计了一款带有通用AHB总线从机接口的DES IP核,能在500MHz频率的总线下很好地工作,DES模式下加、解密转换速率可达到1.6Gb/s,3DES模式下加、解密转换速率可达到615Mb/s.用VCS软件仿真并用DC软件综合后结果均符合设计要求.

     

    Abstract: This paper presents a DES IP core equipped with a AHB Slave Interface.It works perfectly with a bus frequency of 500 MHz.The maximum sustained conversion rate for DES is around 1.6Gb/s.And it is around 615Mb/s for 3DES.After simulating by VCS and synthesizing by DC,results show that it fulfills the design require.

     

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