Abstract: This paper proposes a variable resolution on-chip jitter measurement system which is based on a vernier delay line. In order to eliminate the error introduced by external reference clock, a self-referred architecture is realized by using a one-period delay module. The vernier delay line is composed of digitally controlled delay elements, and the resolution could be set by a selection signal. True single phase clock D flip-flops are adopted in the read-out part to achieve high speed jitter measurement. Compared with traditional methods, the proposed system gains the larger frequency range and the higher measurement resolution, and need not the reference clock. The system is designed in a 0.13 μm CMOS process with 1.5 V supply power. Post-layout simulation results reveal that the system can measure clock jitter various from 100 MHz to 800 MHz with a highest timing resolution of 5.71 ps and a largest range of 1.4 ns.