多核处理器片上可重构Cache系统及其机制设计
The Design of Reconfigurable Cache Scheme in Multi-core Processor
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摘要: 针对多核处理器规模化数据访存与并行线程交叉数据使用的特性, 提出了一种可重构Cache的设计方案, 包含其基本硬件逻辑结构和工作机制; 同时提出了一种可在线动态重构Cache结构配置字生成的DCAC配置方法。实验证明, 上述设计方案配合在线配置方法工作, 能有效实现多核处理器系统根据不同的应用实时地配置共享Cache的组相联度, 使得近处理器内核的Cache系统有效提升了命中率, 在硬件开销增加4.07%的情况下, 缺失代价平均下降约16.13%, 从而达到了多核处理器性能优化的目标。Abstract: To deal with massive and parallel data processing, the paper proposed a design solution of reconfigurable cache for multi-core processor.The work included the design of reconfigurable cache structure and its operation scheme, as well as a reconfiguration context word generation method, named as Dynamic Cache Associativity Configuration(DCAC)method.The experiments verified that with 4.07% overhead in hardware cost, the design solution won a 16.13% reduction of miss penalty in average for the core nearby caches with dynamic cache associativity reconfiguration method.