施展. 一种高速RS码与LDPC级联码编码器设计及硬件实现[J]. 微电子学与计算机, 2010, 27(10): 107-110.
引用本文: 施展. 一种高速RS码与LDPC级联码编码器设计及硬件实现[J]. 微电子学与计算机, 2010, 27(10): 107-110.
SHI Zhan. Design and Implementation of a Fast RS and QC-LDPC Cascade Encoder[J]. Microelectronics & Computer, 2010, 27(10): 107-110.
Citation: SHI Zhan. Design and Implementation of a Fast RS and QC-LDPC Cascade Encoder[J]. Microelectronics & Computer, 2010, 27(10): 107-110.

一种高速RS码与LDPC级联码编码器设计及硬件实现

Design and Implementation of a Fast RS and QC-LDPC Cascade Encoder

  • 摘要: 提出了一种高速RS+QC-LDPC级联码编码器, 介绍了这种级联码在FPGA平台上的实现方法, 并对其性能进行了评估.重点介绍了RS+QC-LDPC级联码的各种优化技术, 如基于二次扩展的QC-LDPC编码方法, 采用交织技术, 合理的搭配RS码和QC-LDPC码的码长、码率以达到最好的性能.经过优化, 级联码编码器的吞吐量可以达到2.25Gbit/s以上.

     

    Abstract: In this paper, a novel design of RS+QC-LDPC cascade encoder is presented, furthermore, the based FPGA implementation of the encoder is introduced.The throughput of cascade encoder surpasses 2.25G bit/s with using several optimization techniques, such as duplex expansion QC-LDPC code, interleave coded and reasonable code length and code rate.

     

/

返回文章
返回