裴希杰, 田泽, 郑新建, 张骏, 许宏杰, 刘宁宁. 一种流水处理图元建立电路的设计与实现[J]. 微电子学与计算机, 2019, 36(8): 10-13, 18.
引用本文: 裴希杰, 田泽, 郑新建, 张骏, 许宏杰, 刘宁宁. 一种流水处理图元建立电路的设计与实现[J]. 微电子学与计算机, 2019, 36(8): 10-13, 18.
PEI Xi-jie, TIAN Ze, ZHENG Xi-jian, ZHANG Jun, XU Hong-jie, LIU Ning-ning. Design and implementation of a pipeline primitives assembly circuit[J]. Microelectronics & Computer, 2019, 36(8): 10-13, 18.
Citation: PEI Xi-jie, TIAN Ze, ZHENG Xi-jian, ZHANG Jun, XU Hong-jie, LIU Ning-ning. Design and implementation of a pipeline primitives assembly circuit[J]. Microelectronics & Computer, 2019, 36(8): 10-13, 18.

一种流水处理图元建立电路的设计与实现

Design and implementation of a pipeline primitives assembly circuit

  • 摘要: 为了提高图形处理器的图形绘制能力, 本文设计了一种能够流水处理的图元建立电路, 实现了OpenGL定义的9种图元到点、线和三角形简单图形的转换, 可有效降低图形流水线后续单元任务的复杂度, 提高图形绘制性能.通过虚拟仿真和FPGA原型验证确认, 实现了基本图元的建立功能, 频率能够达到400 MHz以上, 三角形建立峰值可达380 M/s.

     

    Abstract: Primitives is a basic unit for graphic processing. To improve the performance for GPUs a primitive assembling circuit is presented. The circuit has a simple structure, pipelining and can convert all primitivesdefined by OpenGL to separate point, line or triangle. The circuit can reduce the complexity of the flowing unit task and improve the performance of drawing. The verification of the circuit is completed by module level simulation verification and FPGA prototype verification, the results show that the design is function and the frequency can reach 400MHz and the peak value of triangle assembly can reach 380M/s.

     

/

返回文章
返回