Abstract: High speed frequency divider is widely used in PLL-based frequency synthesizers.A configurable pulse-swallow divider with the range from 2 to 256 is presented in this article.The divider based on an improved divided-by-2 architecture without any conventional dual-modulus prescaler is designed to reduce power consumption and chip area.Implemented in 65nm CMOS process,post-layout simulation results show that the divider can work as high as 6GHz stably while the max power dissipation is no greater than 1.3mW.