Abstract: A low-power successive approximation register analog -to -digital converter with hybrid encoding DAC is proposed in this paper.To decrease the glitch of the charge redistributed DAC,the split-capacitor DAC adopt the hybrid code.To increase the matching accuracy and reduce the influence of parasitic effect of DAC,some matching techniques are adopted in the layout design of the proposed DAC and capacitor.The SAR ADC is fabricated and verified in GF(Global Foundry) 0.35 μm CMOS process.The measurement results have shown that at 500 KSPS, the INL and DNL are -0.6~0.4 LSB and -0.2~0.7 LSB,respectively,the SNDR is 54.13 dB and the ENOB is 8.7 bits.The total circuit consumption is 537.9 μW.