Abstract: This work puts forward a new fully-pipelined hardware architecture for ray traversal and ray-triangle intersection testing.Through using a restart based traversal heuristic,the proposed work support two level pipelined operation,i.e.coarse-grain pipeline at task level and fine-grain pipeline inside the traversal process.The paper also introduces an improved method to perform ray-triangle intersection test at a reduced numbers of floating point computations.When implemented on FPGA,the proposed architecture enables processing 80 million rays per second when running at a 100 MHz clock.