DTMB接收机中3780点FFT处理器的设计
Design of 3780 Point FFT Processor for DTMB Receiver
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摘要: 提出了一种适合于DTMB接收机使用的FFT处理器的设计方法.该处理器基于混合基算法, 素因子分解法和WFTA算法, 采用动态截位法来保证精度与减小功耗和面积.FPGA验证表明:在输入输出均为13位时, 该处理器的信噪比达到了60.4dB, 运行最高频率达到84.48MHz, 满足了DTMB接收机对FFT处理器的精度要求和速度要求.Abstract: Present a design of FFT processor for DTMB receiver.This processor is based on mixed radix algorithm, prime factor algorithm and WFTA.Dynamic scaling algorithm is also employed to achieve high precision and to reduce the power and area.The verification of FPGA shows that SNR of the processor is 60.4 dB and the max frequency is 84.48 MHz when both of the data width of input and output is 13 bits, which has meet the requirement of precision and frequency of DTMB receiver respectively.
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