Abstract: In order to reduce the delay and power during multiplying, a Parallel Row Bypassing (PRB) multiplier based on the row bypassing multiplier was designed in this paper.It can greatly reduce the number of partial products and the operating delay by recoding the multiplier and parallel outputting the partial products.For decreasing the logic units and reducing the power, the PRB multiplier was implemented by the finite state automaton.This design was simulated in Quartus, and the simulation result shows that the PRB multiplier has a great improvement in the whole performance.