基于商用工艺的抗辐射标准单元库设计
Rad-Hard Standard Cell Library Design Based on Commercial Process
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摘要: 为了实现与商用CMOS工艺兼容和最好的抗辐射效果,采用环形栅结构消除NMOS管中由总剂量效应引起的漏电流,采用保护环减轻单粒子闩锁效应和消除电势不同的有源区间场区漏电流,采用双互锁存储单元结构提高时序单元的抗单粒子翻转能力.利用这些加固方法,实现了在0.18μm CMOS logic工艺下小规模、混合高度、高密度标准单元库设计.利用数字集成电路前后端工具验证单元库设计,结果表明此设计内容完全可行.Abstract: Enclosed-gate layout can eliminate current leakage caused by TID in a NOMSFET. Guard ring can alleviate SEL and eliminate field current leakage through two active areas with different potentials. DICE can weaken SEU in sequential cells. The three methods above can help us achieve the purpose of compatibility with commercial process and best rad-hard effect. A small, mixed-height and high density standard cell library is designed based on 0. 18 μm CMOS logic process using the three methods above. Validation of the library is implemented with Digital IC tools and the coming results get well.
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