数字IP核的IEEE Std1500外壳架构设计研究

Research on IEEE Std1500 Wrapper Design for Digit IP Core

摘要: IP核可测试性架构的多样性、互不兼容性给SoC的测试带来不便,IEEE Std1500针对此问题提出了一种标准的、可配置的可测试性架构,如何设计实现这种架构便成为SoC测试研究的热点问题.基于IEEE Std1500,利用边界扫描技术,结合自行设计的IP核,本文给出标准化架构的设计过程,利用quartus ii平台仿真验证了多种测试指令下设计的有效性.提出的外壳并行配置设计打破传统串行测试的局限性,为实现SoC中IP核的并行测试、缩短测试时间提供新的思路.

Abstract: Because of the diversity of IP-core testability structure, the test of SoC is becoming more and more difficult.Aiming at this, a standardized structure is proposed by IEEE Std1500, how to realize this structure becomes a research of interest.Based on IEEE Std1500 and boundary-scan, taking user-designed IP core for example, one design method of the structure is discussed;By using quartus ii, multi-instruction simulation of structure is done, and the design's validity is proved.Through the design of WPP, a novel method to accomplish parallel test of IP-core is put forward.