张弘, 梁元. 0.13微米CMOS双通道超宽带低噪声放大器设计[J]. 微电子学与计算机, 2012, 29(10): 37-41,46.
引用本文: 张弘, 梁元. 0.13微米CMOS双通道超宽带低噪声放大器设计[J]. 微电子学与计算机, 2012, 29(10): 37-41,46.
ZHANG Hong, LIANG Yuan. 0.13μm CMOS Dual-Channel UWB LNA Design[J]. Microelectronics & Computer, 2012, 29(10): 37-41,46.
Citation: ZHANG Hong, LIANG Yuan. 0.13μm CMOS Dual-Channel UWB LNA Design[J]. Microelectronics & Computer, 2012, 29(10): 37-41,46.

0.13微米CMOS双通道超宽带低噪声放大器设计

0.13μm CMOS Dual-Channel UWB LNA Design

  • 摘要: 本文设计了一款超宽带低噪声放大器,并对设计流程进行分析仿真.该低噪放采用双通道结构,有效的输入阻抗匹配、平稳的增益和低噪声等性能可以同时实现.应用ADS工具TSMC 0.13μm CMOS工艺库的仿真结果表明,其最大功率增益为14.2dB,在8GHz频点的ⅡP3为-4dBm,输入、输出反射系数分别小于-10.2dB和-10.89dB,噪声指数单调下降到1.46dB,并且总功耗和带内最大增益摆幅较低.

     

    Abstract: In this paper, the design and simulation of an ultra-wide band CMOS low noise amplifier (LNA) is reported.By using of dual-Channel topology, the input matching and flat gain as well as low noise are achieved simultaneously.The LNA was simulated by ADS TSMC 0.13 μm CMOS design kit, obtaining a maximum gain of 14.2dB and ⅡP3 of-4dBm at around 8GHz.The input return loss is under-10.2dB, meanwhile output counterpart better than-10.89dB.The noise figure (NF) falls to 1.46dB monotonically, and the whole hierarchy consumes fair low power and maximum gain rippling is low.

     

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