Abstract: The flexibility of the reconfigurable circuit is an absolute advantage in the circuit, but its circuit interconnection resources are limited, and the utilization of PE (Processing Element) resources is low. The downward fully interconnected reconfigurable array structure realizes full connection between each PE and the next row of PEs in the array, improving PE resource utilization and overall data processing speed. This design uses modelsim and quartus to perform functional simulation and comprehensive downloading. The results show that the reconfigurable data stream processing unit can be reconfigurable in various configurations. By verifying the mapping of the FFT algorithm on the fully interconnected reconfigurable array, the results show that the reconfigurable data stream processing unit successfully implements the expected functionality and meets its timing requirements. The combined results show that 4*4 reconfigurable arrays, including its peripheral circuits, occupy a total of 19, 429 (58%) gate logic resources, supporting a working frequency of 76.07 MHz; a single reconfigurable data stream processor occupies 2565 (8%) The gate logic resource supports a working frequency of up to 108.96 MHz.