伏思昌, 何小海, 卿粼波, 车倜贲. 一种高速LDPC码译码器的设计及实现[J]. 微电子学与计算机, 2015, 32(6): 54-57,61. DOI: 10.19304/j.cnki.issn1000-7180.2015.06.012
引用本文: 伏思昌, 何小海, 卿粼波, 车倜贲. 一种高速LDPC码译码器的设计及实现[J]. 微电子学与计算机, 2015, 32(6): 54-57,61. DOI: 10.19304/j.cnki.issn1000-7180.2015.06.012
FU Si-chang, HE Xiao-hai, QING Lin-bo, CHE Ti-ben. A New Design and Implementation of High Speed LDPC Codes Decoder[J]. Microelectronics & Computer, 2015, 32(6): 54-57,61. DOI: 10.19304/j.cnki.issn1000-7180.2015.06.012
Citation: FU Si-chang, HE Xiao-hai, QING Lin-bo, CHE Ti-ben. A New Design and Implementation of High Speed LDPC Codes Decoder[J]. Microelectronics & Computer, 2015, 32(6): 54-57,61. DOI: 10.19304/j.cnki.issn1000-7180.2015.06.012

一种高速LDPC码译码器的设计及实现

A New Design and Implementation of High Speed LDPC Codes Decoder

  • 摘要: 针对目前低密度奇偶校验(LDPC)码译码复杂度大、速率低、占用资源多的问题,深入研究了LDPC码的译码算法.在加性高斯白噪声(AWGN)信道下,对适合硬件实现的最小和译码算法进行了仿真,得到了最佳的量化方案和译码迭代次数.在两种改进的最小和译码算法的基础上,设计出一种新型的LDPC码部分并行译码器,并在Xilinx公司的FPGA XC5VLX110T上完成了算法的实现和时序的优化.经测试,该译码器的吞吐量达到152 Mb/s.

     

    Abstract: Considering the code decoding complexity, low decoding rate, resource-intensive of LDPC,the decoding algorithm of LDPC codes is studied.The min-sum algorithm is simulated under Matlab, which is based on Additive White Gaussian Noise (AWGN) channel, and the best quantization scheme and the number of iterations are obtained. Then combining two improved min-sum algorithm, designs a new partly parallel LDPC code decoder is designed. The decoder has been realized on Xilinx's FPGA XC5VLX110T. According to timing sequence optimization, the decoder's throughput is up to 152 Mb/s.

     

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