Abstract: In orde to overcome the serious soft error and the high power generated by hardening in deep sub-micro, a new TCAM architecture is improved, which is based on scrubbing technology of DRAM. The cascade NAND-TCAM decrease is used to system power. Some 2-bit errors are corrected by double Hamming circuits dividing TCAM into two parts and decoder error correction circuits match-line. 3T-DRAM cell reduced the complexity caused by Hamming error correction circuits. Results show that this architecture has greater immunity to 1-bit upset and can correct some 2-bit errors. System search power increases only 29.8% comparing with unhardened circuits and the speed of writing and searching do not get affection. It is especially attractive for utilizing and researching of low-power and high-immunity TCAM.