Abstract: In response to the challenges of large area consumption, slow speed, and low computational efficiency found in the hardware implementation of the Softmax function, an efficient calculation method and hardware circuit design have been developed. A sparse maximum value calculation approach is proposed, which only calculates and stores effective input values, improving computational efficiency by employing dynamic shifting to update the maximum value within the pipeline. Additionally, the piecewise linear fitting algorithm is refined to eliminate the need for multipliers, thus reducing hardware resource consumption. Field-Programmable Gate Array(FPGA)-based speech recognition experiments demonstrate that the proposed method decreases exponent storage requirements by 60% and computation time by 50%. Furthermore, a logic synthesis experiment conducted using 45 nm Complementary Metal Oxide Semiconductor(CMOS) technology shows that the Softmax function implementation achieves 14% improvement in circuit performance and 51% reduction in area compared to previous works.