Abstract: Computing-In-Memory (CIM) has been proved to have great potential for convolution of Artificial Intelligent (AI) neural networks. Among them, memory array-based multi-bit memory computing is expected to become an effective means to solve the "memory wall" due to its writing speed and compatibility with Complementary Metal Oxide Semiconductor (CMOS ) process. However, the current multi-bit in-memory computing circuit architecture is facing the problem of high output delay and high energy consumption, mainly due to the performance constraints of traditional sensitive amplifiers. This paper presents a Low-delay Low-power Multi-bit Current-mode Sense Amplifier (LLM-CSA), through the function optimization strategy of reducing the number of working states of the traditional CSA circuit and simplifying the working sequence, and adopting the circuit design idea of the new low detection module, the output delay can be systematically reduced and the energy consumption can be optimized at multiple levels. The function and delay-energy consumption of the proposed LLM-CSA are simulated and validated by using the Midcore International 40 nm low leakage logic process (SMIC40 nm LL) and the Cadence circuit design platform. Through comparative analysis, it is found that the output delay of LLM-CSA is 1.42 times lower and the energy consumption is 1.56 times lower than that of traditional CSA. Further, the performance of the proposed LLM-CSA is compared and verified with a memory array multi-bit in-memory computing architecture with 4 bit input, 4 bit weight and 11 bit output: the new architecture has 1.18 times lower latency and 1.03 times lower energy consumption than the traditional CSA-based in-memory computing system. The proposal of LLM-CSA has certain theoretical and practical significance to promote the design idea of sensitive amplifier and the development of memory array memory computing architecture.