吴嘉祺,姚思远,刘智,等.一种基于有源滤波电路的高PSRR低噪声LDO电路设计[J]. 微电子学与计算机,2024,41(2):67-75. doi: 10.19304/J.ISSN1000-7180.2023.0078
引用本文: 吴嘉祺,姚思远,刘智,等.一种基于有源滤波电路的高PSRR低噪声LDO电路设计[J]. 微电子学与计算机,2024,41(2):67-75. doi: 10.19304/J.ISSN1000-7180.2023.0078
WU J Q,YAO S Y,LIU Z,et al. A design of high PSRR low noise LDO circuit based on active filter circuit[J]. Microelectronics & Computer,2024,41(2):67-75. doi: 10.19304/J.ISSN1000-7180.2023.0078
Citation: WU J Q,YAO S Y,LIU Z,et al. A design of high PSRR low noise LDO circuit based on active filter circuit[J]. Microelectronics & Computer,2024,41(2):67-75. doi: 10.19304/J.ISSN1000-7180.2023.0078

一种基于有源滤波电路的高PSRR低噪声LDO电路设计

A design of high PSRR low noise LDO circuit based on active filter circuit

  • 摘要: 为了减少低压差线性稳压器(Low Dropout Regulator, LDO)电路中的噪声以及输入电压携带的纹波对输出电压精度所带来的影响,提出了一种基于有源滤波思想的优化LDO噪声和电源抑制比(Power Supply Rejection Ratio, PSRR)的电路设计技术,在不考虑功耗以及压差的条件下,采用多级稳压设计以大幅提升LDO的电源抑制比。通过前级LDO电路对输入电压进行稳压,形成二次电源后对后续电路进行供电,同时在后级LDO的基准端加入一级额外的稳压电路进行稳压,并通过低功耗RC滤波器和跨导放大器以减少环路噪声。 此外,电路还加入了低噪声前馈电路以及快速启动电路提高LDO的响应速度。基于0.18 μm BCD工艺,在5 V输入3.3 V输出,负载电流为10 mA的仿真验证下,测得整体电路在1 kHz时PSRR达到−110 dB,同时在10 ~ 100 kHz下其噪声仅为5.3 μVrms。同时,通过改变基准端负载电容以及负载电流对LDO的PSRR以及噪声进行仿真,其结果均满足设计需求,有效提高了LDO输出电压的精度。

     

    Abstract: In order to reduce the noise in the Low Dropout Regulator(LDO) circuit and the ripple carried by the input voltage on the output voltage accuracy, a circuit design technique based on the idea of active filtering is proposed to optimize LDO noise and Power Supply Rejection Ratio(PSRR), and a multi-stage regulated design is adopted to greatly improve the PSRR of LDO without considering power consumption and dropout voltage. The input voltage is regulated by the pre-LDO circuit, and the subsequent circuit is powered after a secondary power supply is formed, and an additional stage of regulation circuitry is added to the reference of the post-stage LDO to regulate the voltage and reduce loop noise through a low-power RC filter and transimpedance amplifier. In addition, a low-noise feedforward circuit and a fast start-up circuit are added to improve the response speed of the LDO. Based on the 0.18 μm BCD process, under the simulation verification of 5 V input 3.3 V output and 10 mA load current, the overall circuit is measured to reach −110 dB PSRR at 1 kHz, and its noise is only 5.3 μVrms at 10 - 100 kHz. At the same time, by simulating the PSRR and noise of the LDO by changing the load capacitance and load current of the reference, the results meet the design requirements and effectively improve the accuracy of the LDO output voltage.

     

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