基于层级多尺度方法的TSV晶圆翘曲预测模型研究

孙国立; 秦飞; 代岩伟; 李宝霞

doi:10.19304/J.ISSN1000-7180.2022.0667

基于层级多尺度方法的TSV晶圆翘曲预测模型研究

doi: 10.19304/J.ISSN1000-7180.2022.0667

1.
北京工业大学材料与制造学部, 北京 100124
2.
西安微电子技术研究所, 陕西西安 710054

基金项目: 国家自然科学基金（12272012）；西安微电子技术研究所创新基金资助项目（771CX2020001）

详细信息

作者简介:
孙国立：男,（1998-）,硕士研究生. 研究方向为电子封装技术与可靠性

代岩伟：男,（1988-）,副教授. 研究方向为电子封装技术与可靠性研究、疲劳断裂及结构完整性

李宝霞：女,（1977-）,副总工艺师,博士生导师. 研究方向为TSV三维立体集成封装技术

通讯作者:
男,（1965-）, 教授, 博士生导师. 研究方向为微电子封装技术与可靠性研究.E-mail：qfei@bjut.edu.cn

中图分类号: TN
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出版历程
- 收稿日期: 2022-10-26
- 修回日期: 2022-12-03
- 网络出版日期: 2023-01-18

Prediction of TSV wafer warpage based on hierarchical multiscale method

1.
Faculty of Materials and Manufacturing, Beijing University of Technology, Beijing 100124, China
2.
Xi’an Microelectronics Technology Institute, Xi’an 710054, China

摘要

摘要:
随着电子封装技术的发展,以晶圆级封装为代表的先进封装技术对集成密度、封装尺寸,及其制造和服役可靠性提出了更高的要求. TSV晶圆封装结构具有典型的结构多尺度特征,这对有限元模型的建立带来很大挑战. 为此,本文提出了一种层级多尺度方法,并验证了所提方法的有效性. 围绕上述研究内容,首先,阐明了层级多尺度方法的原理和计算流程；其次采用层级多尺度方法建立了不同TSV晶圆封装工艺下的有限元模型,模拟研究了TSV转接板工艺制程中晶圆的翘曲演化,并与实验结果相对比；最后,研究了分区数量对层级多尺度方法精度的影响. 研究结果表明,计算规模相当情况下,随着分区数量的增加,计算误差明显降低. 与实验结果的对比表明,该方法有相对较高的晶圆翘曲预测精度. 此外,本文发展的层级多尺度方法具有一定的可移植性,可以应用到其它同类具有多尺度特征的封装结构可靠性分析中,为解决大规模晶圆级封装翘曲预测问题提供了一种新的解决思路.
- TSV晶圆 /
- 封装 /
- 层级多尺度方法 /
- 翘曲 /
- 有限元模型
Abstract:
With the development of electronic packaging technology, wafer-level packaging is one of the representative advanced packaging methods which puts higher requirements on the integration density of the package, package size, and reliability. However, during the packaging processes, excessive wafer warpage is one of the crucial challenges to affect packaging reliability. The TSV wafer packaging structure presents typical multiscale characteristics, which poses a great challenge on the establishment of finite element models. To this end, a hierarchical multiscale approach is proposed in this paper and the effectiveness of the proposed method is verified. First, the rationale and computational process of the hierarchical multiscale approach is elucidated. Finite element model was established using the hierarchical multiscale method to simulate the warpage evolution during the TSV interposer manufacturing processes, and the simulation results agreed quite closely to the experimental results. Finally, the effect of the hierarchical multiscale approach on the accuracy of the model was investigated. The results of the study show that the computational error decreases significantly with the increase of the number of partitions for a comparable computational size. Compared with the experimental results, it shows that the method can effectively improve the predicting accuracy on wafer warpage. In addition, the developed hierarchical multiscale method is portable and can be applied to other packaging structure featuring with multiscale characteristics, providing a solution to the problem of large-scale electronic packaging.
- TSV wafer /
- Electronic packaging /
- Hierarchical multiscale method /
- Warpage /
- Finite element model

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图 1 TSV晶圆封装结构

Figure 1. The packaging structure of TSV wafer

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图 2 层级多尺度方法分析流程

Figure 2. Analysis process of hierarchical multiscale method

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图 3 四分之一有限元模型

Figure 3. Quarter finite element model

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图 4 基于层级多尺度方法的生死单元模拟过程

Figure 4. Simulation process of element birth and death technology based on hierarchical multiscale method

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图 5 各载荷步对应的工艺温度

Figure 5. Process temperature corresponding to each load step

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图 6 等效模型

Figure 6. Equivalent model

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图 7 全网格模型

Figure 7. Full meshed model

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图 8 等效模型与全网格模型Z向位移对比

Figure 8. Comparison of Z-directional displacement of equivalent model and the full meshed model

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图 9 工艺过程中TSV晶圆翘曲演化

Figure 9. TSV wafer warpage evolution during the process

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图 10 解键合后晶圆翘曲测量值

Figure 10. Wafer warpage measurement after debonding process

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图 11 分区数量对晶圆翘曲值的影响

Figure 11. Effect of the number of partitions on wafer warpage evolution

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图 12 分区数量对预测精度的影响

Figure 12. Impact of the number of partitions on prediction accuracy

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表 1 封装结构尺寸参数

Table 1. Dimensions of packaging structure

结构	几何尺寸	结构	几何尺寸
Wafer晶圆	8吋	PI2厚度	15 μm
Wafer厚度	730 μm	TSV高度	200 μm
转接板长×宽	32.66 mm×25.16 mm	SiO₂厚度	2.5 μm
PI1厚度	5 μm	BPI1/BPI2厚度	15 μm
M1/M2厚度	5 μm	BM1厚度	5 μm

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表 2 TSV转接板主要工艺制程

Table 2. Main process of TSV interposer

	工艺步
1	刻蚀晶圆，TSV孔径20 μm，TSV刻蚀深度200 um，TSV开孔率0.23%
2	室温下正面RDL1电镀Cu，厚度5±1.5 μm， RDL1金属覆盖率57%
3	正面PI1（阻焊层）图形化，PI1（阻焊层）厚度10±2 um，PI1（阻焊层）固化最高温度为210℃
4	正面RDL2电镀Cu，厚度5±1.5 μm， RDL2金属覆盖率19.26%
5	正面PI2（阻焊层）图形化，PI2（阻焊层）厚度15±3 um，PI2（阻焊层）固化最高温度为210℃
6	背面键合至另一片玻璃晶圆，键合胶厚度 80-100 μm，固化条件温度为210℃
7	背面旋涂并图形化PI胶，烘烤固化后形成阻焊层，固化最高温度仍为210℃
8	背面旋涂并图形化PI胶，烘烤固化后形成阻焊层BPI1，厚度15 μm，固化温度210℃
9	激光解键合，切割晶圆

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表 3 材料参数^[17-18]

Table 3. Material properties

材料	弹性模量/GPa	泊松比	CTE/ （ppm/℃）	玻璃转化温度/℃
玻璃	73.6	0.23	3.5	/
铜	117	0.35	17	/
硅	131	0.3	2.8	/
二氧化硅	76.7	0.2	0.6	/
临时键合胶	1.2（E1）/ 0.4（E2）	0.38	45（CTE1）/ 90（CTE2）	120
聚酰亚胺	2.5	0.28	54	/

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表 4 TSV转接板功能层和各区域含铜率

Table 4. TSV interposer functional layer and copper content in each area

	图形区	测试区1	测试区2	测试区3
TSV层	0.78%	0.74%	0.73%	0.35%
M1层	77.23%	45.00%	11.20%	11.00%
PI1层	0.48%	1.20%	0.60%	2.10%
M2层	24.43%	16.00%	11.20%	6.00%
PI2层	3.76%	5.00%	8.85%	5.70%
BPI1层	0.14%	1.00%	2.00%	2.00%
BM1层	24.31%	13.00%	11.20%	11.00%
BPI2层	9.58%	10.00%	5.30%	5.30%

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表 5 等效材料参数

Table 5. Equivalent material properties

	方向	弹性模量 /GPa	泊松比	剪切模量 /GPa	CTE/ （ppm/℃）
TSV层	z	130.89	0.30	50.33	2.90
TSV层	x,y	130.88	0.30	50.32	2.92
M1层	z	90.93	0.04	3.98	17.23
M1层	x,y	10.24	0.36	3.77	32.82
PI1层	z	3.04	0.23	0.98	47.25
PI1层	x,y	2.51	0.31	0.96	57.92
M2层	z	30.47	0.03	1.28	19.29
M2层	x,y	3.29	0.38	1.19	57.22
PI2层	z	6.80	0.11	1.01	30.09
PI2层	x,y	2.60	0.37	0.95	64.14
BPI1层	z	2.66	0.26	0.98	51.72
BPI1层	x,y	2.50	0.29	0.97	55.42
BM1层	z	30.33	0.03	1.28	19.31
BM1层	x,y	3.28	0.38	1.19	57.28
BPI2层	z	13.47	0.06	1.08	22.31
BPI2层	x,y	2.76	0.38	1.00	63.33

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