Abstract: A general-purpose CNN (Convolutional Neural Networks) accelerator is proposed to solve the problems of the current AI-specific accelerators such as complex design and memory bottlenecks. Its RISC (Reduced Instruction Set Computer) instruction set supports efficient mapping of different types of convolutional neural networks to hardware accelerators. The convolution calculation module is a reconfigurable 3D systolic array composed of multiple basic operation units, which supports two-dimensional convolution calculations of different sizes. The scale of the 3D systolic array can be configured according to needs, which is suitable for different parallel acceleration requirements. To further improve the computing power of the accelerator by easing its memory bottlenecks, a multi-level cache structureis introduced into the input module, which can realize high-speed reading of off-chip data. A multi-level data accumulation structure based on the ping-pong architecture is designed to realize the cache of convolution calculation results in the output module. The proposed architecture is implemented on an FPGA chip, and the experimental results show that the architecture achieves competitive performance with less computing resources and lower power consumption, and is more versatile.