一种宇航微系统SiP计算机模块的分析及设计

华虹; 刘鸿瑾; 李宾; 吴宪祥; 孙印昂

doi:10.19304/J.ISSN1000-7180.2022.0512

一种宇航微系统SiP计算机模块的分析及设计

doi: 10.19304/J.ISSN1000-7180.2022.0512

华虹^{1, 2},
刘鸿瑾^2, ,,
李宾²,
吴宪祥¹,
孙印昂³

1.
西安电子科技大学空间科学与技术学院, 陕西西安 710126
2.
北京轩宇空间科技有限公司, 北京 100080
3.
西安电子科技大学广州研究院, 广东广州 510555

基金项目: 宇航级高性能处理器芯片研制及示范应用（Z211100004421016）

详细信息

作者简介:
华虹：女,（1998-）,硕士研究生.研究方向为高可靠系统级封装设计

李宾：男,（1985-）,博士,高级工程师.研究方向为高可靠微系统模块设计及验证

吴宪祥：男,（1980-）,博士,副教授.研究方向为模式识别,计算机视觉等

孙印昂：男,（1998-）,硕士研究生.研究方向为低功耗SoC设计

通讯作者:
男，（1980-），博士，研究员.研究方向为SoC和SiP等微小型化电子系统技术.E-mail：lhjbuaa@163.com

中图分类号: TN402
计量
- 文章访问数: 55
- HTML全文浏览量: 26
- PDF下载量: 11
- 被引次数: 0
出版历程
- 收稿日期: 2022-08-25
- 修回日期: 2022-11-02
- 网络出版日期: 2023-01-18

Analysis and design of a SiP computer module for aerospace microsystem

1.
School of Aerospace Science and Technology, Xidian University, Xi’an 710126, China
2.
Beijing Xuanyu Space Technology Co., Ltd., Beijing 100080, China
3.
Guangzhou Institute of Technology, Xidian University, Guangzhou 510555, China

摘要

摘要:
针对航天器用元器件高密度、高性能、小型化的特点,设计了一种应用于卫星及空间站平台的宇航微系统SiP（System-in-Package）计算机模块. SiP模块设计需解决信号干扰、供电系统不稳定以及散热性能差等问题,所以本文在SiP模块的封装、布局、层叠、布线设计方面,分别通过使用高热导率封装材料、加强散热性的封装形式以及对芯片采用上下腔布局的方式增强系统的散热能力,并采用低串扰设计、低阻抗设计提升系统中信号和电源的稳定性. 通过仿真校验,该模块在125 ℃的条件下,实际工作温度仅上升25.3 ℃；最复杂的信号线之间的串扰低至−37.57 dB；各电源域的直流压降、电流密度以及阻抗参数值均优于参考指标.
- 系统级封装（SiP） /
- 陶瓷封装 /
- 信号完整性（SI） /
- 电源完整性（PI） /
- 热分析
Abstract:
Aiming at the characteristics of high density, high performance and miniaturization of components used in spacecraft, a computer module of aerospace micro system SiP applied to satellite and space station platform is designed in this paper. The design of SiP module needs to solve the problems such as signal interference, unstable power supply system and poor heat dissipation performance. Therefore, in terms of packaging, layout, lamination and wiring design of SiP module, this paper enhances the heat dissipation capacity of the system by using high thermal conductivity packaging materials, enhancing heat dissipation packaging forms and adopting upper and lower cavity layout for chips, and adopts low crosstalk design Low impedance design improves the stability of signal and power supply in the system. Through simulation and verification, the actual working temperature of the module only increases by 25.3℃ under the condition of 125℃; the crosstalk between the most complex signal lines is as low as −37.57 dB; the DC voltage drop, current density and impedance parameters of each power domain are better than the reference indexes.
- System-in-Package /
- ceramic packaging /
- Signal Integrity /
- Power Integrity /
- thermal analysis

HTML全文

图 1 系统原理框图

Figure 1. System schematic diagram

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图 2 SiP设计步骤

Figure 2. SiP design procedure

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图 3 封装基板等效模型

Figure 3. Substrate equivalent model

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图 4 单面摆件布局示意图

Figure 4. One side decoration layout

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图 5 双面摆件布局示意图

Figure 5. Double-sided decoration layout

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图 6 层叠设计示意图

Figure 6. Schematic diagram of cascading design

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图 7 去耦设计示意图

Figure 7. Schematic diagram of decoupling design

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图 8 蛇形走线示意图

Figure 8. Diagram of serpentine routing

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图 9 JA模型示意图

Figure 9. JA schematic diagram of model

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图 10 125 ℃下，JA裸芯温度云图

Figure 10. JA bare core temperature cloud image at 125 ℃

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图 11 串扰仿真结果图

Figure 11. Crosstalk simulation result diagram

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图 12 1.2V电源域压降及电流密度仿真图

Figure 12. 1.2V DC drop/current density simulation diagram

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图 13 3.3V电源域压降及电流密度仿真图

Figure 13. 3.3V DC drop/current density simulation diagram

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图 14 阻抗参数曲线图

Figure 14. Impedance parameter curve

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表 1 1.2 V电源网络阻抗分析结果

Table 1. 1.2 V impedance analysis results

VCC_1.2V 实际最大阻抗目标阻抗

SoC 0.223ohm@53 MHz 0.23 ohm
ASIC 0.139ohm@50 MHz 6 ohm

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表 2 3.3 V电源网络阻抗分析结果

Table 2. 3.3 V impedance analysis results

VCC_3.3V 实际最大阻抗目标阻抗

SoC 0.228ohm@100 MHz 1.1 ohm
FLASH 1.314ohm@100 MHz 11 ohm
SRAM 0.279ohm@100 MHz 1.65 ohm
ASIC 0.124ohm@100 MHz 2.2 ohm

下载: 导出CSV

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