Abstract: Single-precision floating-point division is commonly used in the fields of image processing, artificial intelligence scientific computing. An exact floating-point divider conforming to the IEEE-754 standard is designed based on the Taylor series expansion for polynomial approximation algorithm. To obtain the results of faithful rounding, all errors in the calculation process are analyzed, and the signal bit width of coefficients and intermediate result is designed. To get exact results, a calibration method is proposed to calibrate the results with error. To reduce hardware costs, the number of coefficients and the size of the lookup table are controlled by using uniform segmentation. To improve the operating frequency and throughput of the divider, a pipelining method is proposed to implement a five-stage pipeline divider. The post-simulation results show that the maximum delay is 2.35 ns, the area is 0.185 mm², and the power is 69.93 mW.