基于混合踪迹的智能处理器模型和评估分析

郭宏晴; 张盛兵; 李楚曦; 张萌

doi:10.19304/J.ISSN1000-7180.2022.0475

基于混合踪迹的智能处理器模型和评估分析

doi: 10.19304/J.ISSN1000-7180.2022.0475

1.
西北工业大学软件学院, 陕西西安 710129
2.
西北工业大学计算机学院, 陕西西安 710129

基金项目: 航天771所创新基金（771CX2021005）

详细信息

作者简介:
郭宏晴：女,（1998-）,硕士研究生.研究方向为嵌入式软件工程及神经网络加速器仿真模型

张盛兵：男,（1968-）,博士,教授.研究方向为嵌入式微处理器的体系结构研究与微处理器芯片设计

李楚曦：女,（1993-）,博士研究生.研究方向为软硬件协同设计及神经网络加速器设计

通讯作者:
男,（1978-）,博士,副教授.研究方向为计算机架构、智能处理器架构及超大规模集成电路设计.E-mail：zhangm@nwpu.edu.cn

中图分类号: TN492
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- 被引次数: 0
出版历程
- 收稿日期: 2022-08-10
- 修回日期: 2022-11-02

Mixed-trace based simulation model and evaluation for AI processor

1.
College of Software, Northwestern Polytechnical University, Xi’an 710129, Shaanxi, China
2.
College of Computer Science, Northwestern Polytechnical University, Xi’an 710129, Shaanxi, China

摘要

摘要:
近年来,紧耦合智能处理器在资源受限的边缘侧智能处理器应用中受到了广泛关注.但是针对主协处理器在流水线耦合关系做早期设计空间探索时,存在硬件资源关系共享性,数据通路结构复杂多样化以及片上主协计算特征异构性的特点,使得针对智能处理器的仿真评估建模面临着挑战.本文针对紧耦合智能处理器的结构特点,将硬件结构抽象成为软件仿真模型框架,通过对主协处理器基本硬件资源分析,分解指令控制的不同数据通路,设计智能处理器仿真模型.将主处理器与智能协处理器分别采用踪迹仿真和模型解析的方法,引入混合踪迹记录时间戳以统计部件访问信息,结合基于解析的性能评估算法,实现对智能处理器的性能评估.实验结果表明,基于混合踪迹的智能处理器模型和评估分析可以有效的解出智能计算的实际执行结果,并评估得到硬件的性能,包括延时,能耗和功耗等重要参数.
- RISC-V /
- 智能处理器 /
- 踪迹 /
- 仿真模型 /
- 性能评估
Abstract:
In recent years, tightly coupled AI processors have received extensive attention in resource-constrained edge-side intelligent processor applications. But when doing early design space exploration for the main coprocessor in the pipeline coupling relationship. There are the characteristics of shared hardware resource relationship, complex and diverse data path structure, and heterogeneity of on-chip main-cooperative computing features. This makes the simulation evaluation modeling for AI processors facing challenges. This paper focuses on the structural characteristics of tightly coupled AI processors. Abstract the hardware structure into a software simulation model framework. By analyzing the basic hardware resources of the main coprocessor, the different data paths controlled by the instruction are decomposed, and the AI processor simulation model is designed. The main processor and the coprocessor are used in trace simulation and model analysis, respectively. Introduce hybrid trace record timestamps to count widget access information. Then, combined with the analytical performance evaluation algorithm, the performance evaluation of the AI processor is realized. The experimental results show that the AI processor model and evaluation analysis based on the hybrid trace can effectively solve the actual execution results of AI computing, and evaluate the performance of the hardware, including important parameters such as delay, energy and power.
- RISC-V /
- AI processor /
- trace /
- simulation model /
- performance evaluation

HTML全文

图 1 基于混合踪迹的仿真模型架构

Figure 1. Mixed-trace based simulation model architecture

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图 2 流水线时间戳记录

Figure 2. Pipeline timestamp records

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图 3 解析评估器流程图

Figure 3. Flowchart for parsing the evaluator

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图 4 不同网络评估结果

Figure 4. Different network assessment results

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表 1 硬件结构映射参数

Table 1. Hardware architecture mapping parameters

配置部件	配置参数
主处理器结构	标量/超标量处理器流水线,包括寄存器配置、流水线结构等
	存储子系统,包括L1Cache、L2Cache配置、替换策略
	片上互联,包括取数队列表项、存数队列表项、运行指令数、一致性协议、DRAM类型等
协处理器结构	计算并行度
	执行块
	计算模式,计算尺寸,映射方案
	存储容量
	带宽

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表 2 Benchmark的网络参数表

Table 2. Network parameter table for the benchmark

网络名称	参数量	计算量
yolov2-tiny	11 M	2,669 M
AlexNet	60 M	724 M
VGG16	138 M	15 M
ResNet18	25 M	1,942 M
ResNet50	25 M	4,140 M

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表 3 网络配置参数

Table 3. Network configuration parameters

网络参数	参数含义
层信息	网络总层数、当前层类型、当前层索引
输入信息	输入尺寸、输入数量
输出信息	输出尺寸、输出数量
卷积核信息	卷积核尺寸、卷积核数量、滑步大小
填充	填充宽度
归一化	当前层是否需要BN
输入数据位宽	输入数据位宽
池化	当前层是否进行了池化操作

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表 4 实验约束参数设置表

Table 4. Experiment constraint parameter settings

配置参数	参数含义	实验使用参数
配置参数	参数含义	实验一	实验二
Freq	时钟频率	100 Mhz	100 Mhz
Para	并行度	64	128
Bandwidth_total	最大带宽	64 Gb/s	64 Gb/s
DSP_total	片上DSP总数量	2020	2020
BRAM_total	片上存储使用容量	26.5 Mb	26.5 Mb

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表 5 评估模型精度比较

Table 5. Evaluate model accuracy comparisons

	评估数据	硬件数据	误差
延时	333.99 ms	362.8 ms	7.94%
能耗	2.33 J	2.225 J	4.94%
功耗	6.99 W	6.147 W	13.71%
功效比	2.63 GOPS/W	2.76 GOPS/W	4.6%

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表 6 ASIC的硬件结构评估结果

Table 6. The results of the hardware structure evaluation of the ASIC

	VGG16	AlexNet	Resnet18	Resnet50
计算量GOP	30.76	1.45	3.6	7.72
吞吐量GOPS	131.81	76.04	113.82	92.51
延时ms	233.37	19.07	31.63	83.45
功耗W	0.411	0.308	0.419	0.223
能耗J	0.096	0.006	0.013	0.019
能效比GOPS/J	1374.2	12945.4	8587.9	4971.1
功效比GOPS/W	240.9	246.9	271.11	415.12

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