Abstract: An on-chip charge pump circuit with fast start and low power consumption for anti-fuse FPGA is proposed. The circuit is based on the Dickson charge pump structure, which is started by high-frequency clock signal to improve the starting speed. After the charge pump output is stable, the low-frequency clock signal is used to hold the charge pump output to reduce the circuit power consumption. The isolation between high voltage and low voltage is realized by adding zero voltage circuit, which solves the output requirements of anti-fuse FPGA under different working modes of charge pump. The spectre results show that under the working voltage of 2.5 V and full load of the whole circuit, the starting time is 13.5 μs. The stable output voltage is 5.43V, the starting current is 1.06 mA and the working current is 184 μA. The start-up time is 36.5 μs faster than the reference, equivalent to 3.7 times, power consumption increased by only 35%. Taping-out with 0.18μm CMOS process, the circuit programming is successful and the function is correct. The results show the feasibility and practicability of this structure.