Abstract: In order to meet the needs of RISC-V platform software debugging in the RISC-V architecture ecosystem, an on-chip debugging system based on the RISC-V debugging protocol is designed and implemented. The system implements and hides the internal register access logic of the debug module through the debug transport module, and simplifies it into a JTAG serial signal to implements the interaction with the host computer. On the basis of the basic debugging function, the direct bus access, program buffer and trigger function based on the trigger module are further implemented, and implements the event sequence trigger function while being compatible with the RISC-V debugging protocol. The on-chip debugging system relies on the self-developed RISC-V processor hardware platform, and performs functional testing through the host software environment composed of GDB and OpenOCD. The comparison with other RISC-V architecture processors and FPGA tests show that the on-chip debugging system is rich in functions and can meet the functional requirements of the current RISC-V platform debugging.