Abstract: As data transfer rates increase, the system demands more and more on the clock signals. Delay locked loops provide multiphase clocks in various high speed communication systems and the BER is affected by the phase accuracy. However, the phase error induced by mismatches of phase detector is increasingly severe as the clock frequency increases. In this study, an self-calibrated scheme of an OTA-based delay locked loop is proposed to solve the problem of inaccurate output clock. The Verilog-A behavioral model of calibrated circuit is given simultaneously. The mismatches of two or-gates in phase detector will cause an output phase shift in the form of offset voltage between the inputs of OTA. And the voltage can be detected, calculated and compensated to the loop. With the calibrated circuit, the input voltage difference of OTA will be zero and the delay of voltage controlled delay line won't change any more when the feedback clock is ideal. As a result, the phase error of output clock can be reduced effectively. The DLL produces a four-phases clock at a frequency range of 10 to 12GHz is implemented in TSMC 40nm CMOS process. A framework to realize the self-calibrated scheme is constructed. The simulation results of circuits associated with models show that the RMS phase error is decreased from 300fs to 30fs.