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一款用于Flash型FPGA的配置电路设计

曹正州 刘国柱 单悦尔 沈广振 涂波 徐玉婷

曹正州, 刘国柱, 单悦尔, 沈广振, 涂波, 徐玉婷. 一款用于Flash型FPGA的配置电路设计[J]. 微电子学与计算机, 2022, 39(11): 118-128. doi: 10.19304/J.ISSN1000-7180.2022.0285
引用本文: 曹正州, 刘国柱, 单悦尔, 沈广振, 涂波, 徐玉婷. 一款用于Flash型FPGA的配置电路设计[J]. 微电子学与计算机, 2022, 39(11): 118-128. doi: 10.19304/J.ISSN1000-7180.2022.0285
CAO Zhengzhou, LIU Guozhu, SHAN Yueer, SHEN Guangzhen, TU Bo, XU Yuting. A configuration circuit design for Flash-based FPGA[J]. Microelectronics & Computer, 2022, 39(11): 118-128. doi: 10.19304/J.ISSN1000-7180.2022.0285
Citation: CAO Zhengzhou, LIU Guozhu, SHAN Yueer, SHEN Guangzhen, TU Bo, XU Yuting. A configuration circuit design for Flash-based FPGA[J]. Microelectronics & Computer, 2022, 39(11): 118-128. doi: 10.19304/J.ISSN1000-7180.2022.0285

一款用于Flash型FPGA的配置电路设计

doi: 10.19304/J.ISSN1000-7180.2022.0285
基金项目: 

国家自然科学基金面上项目 62174150

江苏省自然科学基金面上项目 BK20211040

详细信息
    作者简介:

    曹正州  男,(1982-),高级工程师.研究方向为SRAM型FPGA、FLASH型FPGA和FPGA配置芯片的设计. E-mail: caozhengzhou@163.com

    刘国柱   男,(1980-),博士,高级工程师.研究方向为FLASH器件和存算一体器件的设计

    单悦尔   男,(1979-),博士,研究员.研究方向为自主架构FPGA、DSP和FPGA配置芯片的设计

    沈广振   男,(1990-),硕士,工程师.研究方向为PLL、GTP等模拟电路的设计

    涂波  男,(1985-),工程师.研究方向为PLL、Charge Pump等模拟电路的设计

    徐玉婷   女,(1983-),硕士,高级工程师.研究方向为POR、Bandgap、PLL等模拟电路的设计

  • 中图分类号: TN402

A configuration circuit design for Flash-based FPGA

  • 摘要:

    为了能够为flash型FPGA中的flash开关单元提供稳定的擦除、编程和读取操作电压,基于0.11 μm 2P8M flash工艺,设计了一款用于flash型FPGA的配置电路.根据flash cell的操作条件和flash型FPGA的特点设计了层次化的字线电路、带校验功能的位线电路、低纹波的电荷泵电路、多级的电平转换电路、灵活的衬底电压电路以及配置控制电路.该配置电路是执行配置算法流程的基础,为flash型FPGA配置过程中的flash cell提供了高精度和稳定的操作电压,保证了flash cell在擦除和编程后的阈值电压分布的一致性, 使flash型FPGA的性能得以充分发挥.仿真结果表明:擦除时字线的驱动能力为1.2 mA,输出电压-10.5 V,误差小于±0.1 V,建立时间为11.2 μS; 位线驱动能力为1.2 mA,输出电压8.8 V,误差小于±0.1 V,建立时间为7.5 μS。编程时字线的驱动能力为1.2 mA,输出电压9.8 V,误差小于±0.1 V,建立时间为2.3 μS; 位线驱动能力为4.4 mA,输出电压-8.0 V,误差小于±0.1 V,建立时间为2.5 μS.设计满足了flash cell的操作条件,最终实现对350万门flash型FPGA共26 836 992 bits(2 912 bl*9 216 wl)码流的配置.

     

  • 图 1  配置电路的整体架构图

    Figure 1.  Architecture diagram of the configuration circuit

    图 2  单个flash cell的配置电路图

    Figure 2.  Configuration circuit diagram of asingle flash cell

    图 3  Flash cell的操作条件

    Figure 3.  Operation conditions of the flash cell

    图 4  配置数字控制电路

    Figure 4.  Digital control circuit of configure

    图 5  高压系统结构

    Figure 5.  High voltage system structure

    图 6  正压电荷泵结构

    Figure 6.  Positive voltage charge pump structure

    图 7  负压电荷泵结构

    Figure 7.  Negative voltage charge pump structure

    图 8  正压电荷转移电路

    Figure 8.  Positive voltage charge transfer circuit

    图 9  负压电荷转移电路

    Figure 9.  Negative voltage charge transfer circuit

    图 10  正高压开关

    Figure 10.  Positive high voltage switch

    图 11  负高压开关

    Figure 11.  Negative high voltage switch

    图 12  基准电压和电流电路

    Figure 12.  Reference voltage and current circuit

    图 13  电平转换电路

    Figure 13.  Levelshift circuit

    图 14  擦除操作时电平转换示意图

    Figure 14.  Schematic diagram of levelshift during erasing operation

    图 15  编程操作时电平转换示意图

    Figure 15.  Schematic diagram of levelshift during programming operation

    图 16  层次化的字线架构图

    Figure 16.  Hierarchical word line architecture diagram

    图 17  字线控制中的Bank和Group信号

    Figure 17.  Bank and Group signals in word line control

    图 18  字线控制中的WL信号

    Figure 18.  WL signal in word line control

    图 19  单个flash cell的位线读写控制电路

    Figure 19.  Bit line read and write control circuit of a single flash cell

    图 20  正电荷泵(9.8V)仿真波形

    Figure 20.  Positive charge pump (9.8V) simulation waveform

    图 21  负电荷泵(-8.0 V)仿真波形

    Figure 21.  Negative charge pump (-8.0V) simulation waveform

    图 22  电平转换波形

    Figure 22.  Levelshift waveform

    图 23  擦除电压波形

    Figure 23.  Voltage waveform of erasing

    图 24  编程电压波形

    Figure 24.  Voltage waveformof programming

    表  1  配置电路的性能

    Table  1.   Configure circuit performance

    性能指标 设计目标 仿真结果
    擦除时间/mS 6~10 6~10
    每帧数据编程时间/μS 10~15 10~15
    FPGA配置时间/Minutes 2.5~3.0 2.5~3.0
    字线电压精度/V 擦除时-10.5±0.2编程时9.8±0.2 擦除时-10.5±0.1编程时9.8±0.1
    字线驱动能力/mA 1 1.2
    字线建立时间/μS 擦除时15编程时3 擦除时11.2编程时2.3
    位线(漏)电压精度/V 擦除时8.8±0.2编程时-8.0±0.15 擦除时8.8±0.1编程时-8.0±0.1
    位线(漏)驱动能力/mA 擦除时1编程时4 擦除时1.2编程时4.4
    位线(漏)建立时间/μS 擦除时10编程时3 擦除时7.5编程时2.5
    位线(源)电压精度/V 擦除时8.8±0.2编程时-0.9±0.2 擦除时8.8±0.1编程时-0.9±0.1
    位线(源)驱动能/mA 1 1.2
    位线(源)建立时间/μS 擦除时10编程时1 擦除时7.5编程时0.3
    衬底电压精度/V 擦除时8.8±0.2编程时0 擦除时8.8±0.1编程时0
    衬底驱动能力/mA 1 1.2
    衬底建立时间/μS 擦除时10编程时1 擦除时7.5编程时0.2
    下载: 导出CSV
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出版历程
  • 收稿日期:  2022-05-02
  • 修回日期:  2022-05-20
  • 网络出版日期:  2022-11-29

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