一种应用在50~64Gb/s的SERDES接收机中的DSP的设计与实现

刘敏; 郑旭强; 李伟杰; 刘朝阳; 徐华; 张秋月; 刘新宇

doi:10.19304/J.ISSN1000-7180.2022.0261

一种应用在50~64Gb/s的SERDES接收机中的DSP的设计与实现

doi: 10.19304/J.ISSN1000-7180.2022.0261

刘敏^{1, 2},
郑旭强^2, ,,
李伟杰²,
刘朝阳^{1, 2},
徐华²,
张秋月²,
刘新宇²

1.
中国科学院大学集成电路学院，北京 100049
2.
中国科学院微电子研究所，北京 100029

基金项目:

国家重点研发计划 2018YFB2202302

详细信息

作者简介:
刘敏男，(1995-)，硕士研究生.研究方向为高速串行接口中的DSP的设计与实现的研究

李伟杰男，(1997-)，硕士研究生.研究方向为高速串行接口中的DSP的设计与实现的研究

刘朝阳男，(1995-)，硕士研究生.研究方向为高速串行接口中的CTLE的研究

徐华男，(1997-)，博士研究生.研究方向为高速ADC的研究

张秋月女，(1997-)，硕士研究生.研究方向为高速串行接口中的CTLE的研究

刘新宇男，(1997-)，博士，研究员.研究方向为微波功率模块的研究

通讯作者:
郑旭强(通讯作者) 男，(1983-)，博士，研究员.研究方向为高速串行接口系统的研究. E-mail: zhengxuqiang@ime.ac.cn

中图分类号: TN402
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- 被引次数: 0
出版历程
- 收稿日期: 2022-04-20
- 修回日期: 2022-05-17
- 网络出版日期: 2022-11-29

A 50~64Gb/s DSP used in SERDES receiver

LIU Min^{1, 2},
ZHENG Xuqiang^{2
, ,},
LI Weijie²,
LIU Chaoyang^{1, 2},
XU Hua²,
ZHANG Qiuyue²,
LIU Xinyu²

1.
Schoolof Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
2.
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China

摘要

摘要:
介绍了一种基于4脉冲幅度调制(PAM4)SERDES接收机中的专用数字信号处理器(DSP)，主要解决高速串行接口中在50~64 Gb/s的超高速传输速率和20~30 dB大幅度信道衰减下的数据恢复问题.该DSP的32路并行结构使系统能够处理50~64 Gb/s的高速数据信号; 同时，应用了16-tap的前馈均衡器(FFE)，解决了20~30 dB大幅度信道衰减下的数据恢复问题; 运用了最小均方算法(LMS)的自适应算法与FFE结合使用，使其能够在不同的信道衰减下都能够自适应的找到最佳的高频补偿并消除传输信道所产生的衰减影响和码间干扰(ISI)问题; 同时，为解决传统判决反馈均衡器(DFE)在实现并行结构时带来的反馈环路的时序紧张问题，采用了预判决式结构改良的DFE，其级联在FFE后用来消除剩余的ISI并判决出正确数据信号从而配合FFE均衡恢复出原数据信号.该DSP架构在通过仿真验证后利用28nm CMOS工艺进行了加工制造，通过仿真验证和测试验证发现其能够在50 Gb/s的传输速率和20~30 dB信道衰减下达到良好的均衡效果.最终的DSP芯片面积为2.02 mm²，误码率最低到5.21e-9.
- SERDES接收机 /
- 信道 /
- 数字信号处理器(DSP) /
- 前馈均衡器(FFE) /
- 最小均方算法(LMS)
Abstract:
This paper introduces a special digital signal processor (DSP) in SerDes receiver based on 4-pulse amplitude modulation (pam4). It is mainly committed to solving the data recovery problem in a high-speed serial interface under the ultra-high transmission rate of 50~64gb/s and 20-30db large channel attenuation. The 32 channels parallel structure of this DSP enables the system to process 50~64gb/s high-speed data signals; At the same time, 16 tap feedforward equalizer (FFE) is applied to solve the problem of data recovery under 20~30db large channel attenuation; The adaptive algorithm using the least mean square algorithm (LMS) is combined with FFE, so that it can adaptively find the best high-frequency compensation under different channel attenuation and eliminate the attenuation effect and inter symbol interference (ISI) caused by the transmission channel; At the same time, in order to solve the timing tension of the feedback loop caused by the parallel structure of the traditional decision feedback equalizer (DFE), a DFE with improved pre-decision structure is adopted, which is cascaded after the FFE to eliminate the remaining ISI and determine the correct data signal, so as to cooperate with the FFE to balance and recover the original data signal. This DSP architecture was manufactured by using 28nm CMOS process after simulation verification. Simulation and test verification found that it can achieve a good equalization effect at 50gb/s transmission rate and 20~30db channel attenuation. The final DSP chip area is 2.02 mm², and the bit error rate is as low as 5.21e-9.
- SERDES receiver /
- channel /
- digital signal processor (DSP) /
- feed-forward equalizer (FFE) /
- least mean square algorithm(LMS)

HTML全文

图 1 传统串行FFE

Figure 1. The structure of serial in FFE

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图 2 32路并行架构的16-tap FFE结构图

Figure 2. The structure of 32 channel 16-tap FFE

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图 3 FFE输入数据重组

Figure 3. The combination of FFE input data

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图 4 16-tap FFE求解输出

Figure 4. The output method of 16-tap FFE

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图 5 使用全部乘积因子的LMS算法应用在FFE中的实现

Figure 5. The implementation of LMS in FFE using all product factors

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图 6 利用伪随机的LMS算法应用在FFE中的实现

Figure 6. The implementation of LMS in FFE using random factors

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图 7 在23 dB信道衰减下LMS算法计算出的16-tap FFE系数

Figure 7. The coefficients of 16-tap FFE from LMS algorithm in 23 dB

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图 8 传统串行1-tap DFE结构

Figure 8. The structure of serial in DFE

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图 9 32路并行架构预判决DFE结构框图

Figure 9. The structure of 32 channel pre-decision DFE

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图 10 仿真信道S21参数

Figure 10. The S21 of channel in Simulation

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图 11 33dB下系统均衡结果眼图

Figure 11. The eye diagram in 33dB

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图 12 23dB下系统均衡结果眼图

Figure 12. The eye diagram in 23dB

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图 13 DSP均衡结果的VEC趋势图

Figure 13. The chart of VEC for DSP equalization

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图 14 误码仪电平分布图

Figure 14. The waveform of electrical level from Bit Error Ratio Tester

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图 15 接收机后端版图和芯片图

Figure 15. The layout of receiver

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图 16 芯片测试环境

Figure 16. The environment for test

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