Abstract: Multiphase clock is one of the key modules of integrated circuit. It is widely used in analog-to-digital converter (ADC), time-to-digital converter (TDC) and other circuits. Multiphase clocks are usually generated by delay-locked loops (DLL) or phase-locked loops (PLL). However, DLLs cannot multiply frequency, PLLs suffer from jitter accumulation problems. In addition, DLLs and PLLs usually have high power consumption. To solve these problems, a low power multiplying delay-locked loop (MDLL) is proposed, which uses a low power charge pump structure and a voltage controlled delay line that can be switched to a voltage controlled oscillator to switch the circuit function between DLL and PLL. The MDLL can eliminate jitter accumulation while multiplying frequency.By adding a circuit for preventing false lock, the MDLL work at the right frequency. The circuit is implemented in HHGrace 0.11μm COMS process, and occupies only 0.03mm2. The test results show that the circuit can multiply the input reference clock frequency by 32 x, the output clock frequency range is 54.4MHz to 92.8MHz, and the circuit power consumption is 216μW-312μW. When the output clock frequency is 80MHz, the measured RMS jitter is 116.3ps (0.93%).