Abstract: In VLSI design, the accuracy of timing analysis is very important to guide design optimization for timing closure and performance improvement. In the logic synthesis stage, it is difficult to predict the timing due to the lack of placement, and routing information. To improve the accuracy of timing prediction at the logic netlist-level, wireload model is applied to predict the RC parameters, and the Elmore delay model is also used for timing feature calculation. In model training phase, the timing features of the training set are extracted. Taking the corresponding sign-off timing report as the ground-truth, the random forest algorithm is applied for model training. In our method, three models are constructed, including: wire delay model, wire slew model, and output load model. In inference phase, the testing set under the same process library as the training set is used for prediction evaluation. Compared with the commercial tool PrimeTime, the correlation between the sign-off result and our predicted wire delay and wire slew is increased by 49% and 37%, respectively. In addition, the correlation of our output load is more than 0.99.