赵毅, 陈辉, 刘鹏, 武继刚. 基于互补式忆阻器的多路复用器设计与实现[J]. 微电子学与计算机, 2022, 39(5): 96-103. DOI: 10.19304/J.ISSN1000-7180.2021.1134
引用本文: 赵毅, 陈辉, 刘鹏, 武继刚. 基于互补式忆阻器的多路复用器设计与实现[J]. 微电子学与计算机, 2022, 39(5): 96-103. DOI: 10.19304/J.ISSN1000-7180.2021.1134
ZHAO Yi, CHEN Hui, LIU Peng, WU Jigang. Design and implementation of multiplexer based on complementary resistive switches[J]. Microelectronics & Computer, 2022, 39(5): 96-103. DOI: 10.19304/J.ISSN1000-7180.2021.1134
Citation: ZHAO Yi, CHEN Hui, LIU Peng, WU Jigang. Design and implementation of multiplexer based on complementary resistive switches[J]. Microelectronics & Computer, 2022, 39(5): 96-103. DOI: 10.19304/J.ISSN1000-7180.2021.1134

基于互补式忆阻器的多路复用器设计与实现

Design and implementation of multiplexer based on complementary resistive switches

  • 摘要: 针对现有忆阻器逻辑设计方法所需忆阻器数量较大和操作步骤较多的问题,提出一种基于互补式忆阻器(complementary resistive switches,CRS)的灵活配置同行忆阻器的逻辑设计方法.通过对施加于CRS的高电压设置电压约束,更快速地实现布尔逻辑,并利用该方法实现了四种基本逻辑门,分别是与逻辑(AND)、或逻辑(OR)、非蕴含逻辑(not-material implication,NIMP)和异或逻辑(XOR)门.在此基础上,利用所设计逻辑中蕴含的与逻辑运算和或逻辑运算,设计了2-1和4-1多路复用器电路并提出其实现方法,其中2-1多路复用器可使用3个忆阻器通过2个步骤来实现,4-1多路复用器可使用6个忆阻器通过5个步骤来实现,并通过SPICE仿真来验证该方法的可行性.与忆阻器蕴含逻辑(material implication logic,IMPLY)和忆阻器辅助逻辑(memristor aided logic,MAGIC)设计方法相比,本文所提出的方法在保证输入数据不被破坏的前提下同时减少了忆阻器数量和操作步骤,优化了忆阻器实现的2-1多路复用器与4-1多路复用器性能.

     

    Abstract: Aiming at the problem of large number of memristors and many operation steps required by the existing logic design methods of memristors, a logic design method for flexible configuration of memristors in the same row is proposed, which based on the complementary resistive switches (CRS). By setting constraints on the high voltages applied to the CRS, Boolean logic can be realized more quickly, and four basic logic gates are implemented based on the proposed method, which are AND logic, OR logic, not-material implication (NIMP) logic and XOR logic. Utilizing the AND and OR operations contained in the proposed logic design, the 2-1 and 4-1 multiplexers are designed and the implementations are detailed in this paper, which greatly improves the reusability of the memristor, and simplifies the procedure of operations. Besides, a 2-1 multiplexer is implemented with 3 memristors in 2 steps, and a 4-1 multiplexer is implemented with 6 memristors in 5 steps. The feasibility of the designed multiplexers is verified by SPICE simulations. Compared with other methods which are based on memristor material implication logic (IMPLY) and memristor aided logic (MAGIC), the number of used memristors and the operation steps of the proposed method are reduced without corrupting the input data. Optimized the performance of 2-1 multiplexer and 4-1 multiplexer realized by memristor.

     

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