Abstract: Aiming at the problems of high latency and area overhead in the digital logic design based on memristor, A Double Majority-Inverter-Graph Logic (DMIG) for the memristive logic designisproposed. The proposed logic realizes 2 MIG logic synchronously in one clock cycle. Two different basic logic gates are implemented synchronously by initializing the memristor to different logic states and applying different voltages to both ends of the DMIG. In addition, this paper optimizes the Boolean logic expression of full adder by the logic synthesis method and designs a one-bit full adder based on DMIG. Two different optimization methods are proposed to reduce the performance of delay and area overhead.The proposed DMIG and one-bit full adder are simulated and verified in spice simulation environment by utilizing VTEAM, and the delay and area overhead of the circuit are greatly reduced. The delay optimized adder is realized within 4 memristors and 4 steps, while the area optimized adder is realized within 3 memristors and 5 steps. Compared to the existing logic design work, the proposed design reduces the calculation steps and the number of required memristors, and effectively optimizes the performance of the memristive adder.