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基于RISC-V处理器的TileLink与AXI4总线桥设计与实现

洪广伟 崔超 虞致国 顾晓峰

洪广伟, 崔超, 虞致国, 顾晓峰. 基于RISC-V处理器的TileLink与AXI4总线桥设计与实现[J]. 微电子学与计算机, 2022, 39(4): 100-108. doi: 10.19304/J.ISSN1000-7180.2021.1052
引用本文: 洪广伟, 崔超, 虞致国, 顾晓峰. 基于RISC-V处理器的TileLink与AXI4总线桥设计与实现[J]. 微电子学与计算机, 2022, 39(4): 100-108. doi: 10.19304/J.ISSN1000-7180.2021.1052
HONG Guangwei, CUI Chao, YU Zhiguo, GU Xiaofeng. Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor[J]. Microelectronics & Computer, 2022, 39(4): 100-108. doi: 10.19304/J.ISSN1000-7180.2021.1052
Citation: HONG Guangwei, CUI Chao, YU Zhiguo, GU Xiaofeng. Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor[J]. Microelectronics & Computer, 2022, 39(4): 100-108. doi: 10.19304/J.ISSN1000-7180.2021.1052

基于RISC-V处理器的TileLink与AXI4总线桥设计与实现

doi: 10.19304/J.ISSN1000-7180.2021.1052
基金项目: 

江苏省重点研发计划资助项目 BE2019003-2

中央高校基本科研业务费专项资金项目 JUSRP51510

江苏省研究生科研创新计划项目 KYCX20_1936

详细信息
    作者简介:

    洪广伟    男,(1996-),硕士研究生.研究方向为专用集成电路与系统设计

    通讯作者:

    虞致国(通讯作者)    男,(1979年-),博士,副教授.研究方向是AI芯片、高性能处理器设计. E-mail: yuzhiguo@jiangnan.edu.cn

  • 中图分类号: TP402

Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor

  • 摘要:

    RISC-V是近年提出的一种开源精简指令集架构,TileLink总线是专为RISC-V处理器设计的片上总线.为使RISC-V处理器灵活适配更多已有的AXI4 IP资源,提出一种高效率TileLink与AXI4总线桥设计方案,其中由一系列功能子模块匹配总线间数据传输方式的差异,以流水线传输形式实现数据跨协议的传输,增加总线桥的数据吞吐量.在实现总线桥不同通道间的转换时,采用不同的仲裁策略,在AXI4总线的响应转换过程中,采用固定优先级仲裁,优先转换数据响应,保证系统整体运行效率;在AXI4总线的写数据和读数据事务转换过程中,采用轮询仲裁,保证写数据和读数据的公平性,均衡分配目标通道带宽,提高总线带宽利用率和系统传输效率.从模块级用TileLink随机测试激励对总线桥进行仿真验证,并通过在RISC-V处理器上挂载AXI4接口PCI Express根复合体,从FPGA系统级进行验证,结果表明,设计的总线桥能够正确转换协议,并且能较大提高系统带宽利用率.总线桥在SMIC 55 nm CMOS工艺下进行了ASIC实现,工作频率达714 MHz,版图面积405×405 μm2.

     

  • 图 1  TL/AXI4系统架构

    Figure 1.  TL/AXI4 system architecture

    图 2  TileLinkToAXI4总线桥架构

    Figure 2.  TileLinkToAXI4 bridge architecture

    图 3  AXI4ToTileLink总线桥架构

    Figure 3.  AXI4ToTileLink bridge architectur

    图 4  TL2AXI4模块架构与通道转换

    Figure 4.  TL2AXI4 module architecture and channe conversion

    图 5  AXI42TL模块架构与通道转换

    Figure 5.  AXI42TL module architecture and channel conversion

    图 6  总线桥流水线策略

    Figure 6.  Bus bridge transmission pipeline strategy

    图 7  轮询仲裁实现

    Figure 7.  Design of round robin arbiter

    图 8  TileLinkToAXI4总线桥读、写数据传输波形

    Figure 8.  Read and write data transmission waveform of the TileLinkToAXI4 bus bridge

    图 9  AXI4ToTileLink总线桥读、写数据传输波形

    Figure 9.  Read and write data transmission waveform of the AXI4ToTileLink bus bridge

    图 10  RISC-V处理器及其SoC架构

    Figure 10.  Architecture of RISC-V processor and SoC

    图 11  (a) FPGA验证平台(b) PCIE寄存器值(c) PCIE配置

    Figure 11.  (a) FPGA verification platform, (b) PCIE register result, (c) PCIE configuration

    表  1  PCIE寄存器内存映射

    Table  1.   PCIE register memory map

    寄存器地址 描述
    0x000-0x12F PCIe Configuration Space Header
    0x130 Bridge Info Register
    0x134 Bridge Status and Control Register
    0x138 Interrupt Decode Register
    0x13C Interrupt Mask Register
    0x140 Bus Location Register
    0x144 PHY Status/Control Register
    0x148 Root Port Status/Control Register
    0x14C Root Port MSI Base Register 1
    0x150 Root Port MSI Base Register 2
    0x154 Root Port Error FIFO Read Register
    0x158 Root Port Interrupt FIFO Read Register 1
    0x15C Root Port Interrupt FIFO Read Register 2
    下载: 导出CSV
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出版历程
  • 收稿日期:  2021-08-25
  • 修回日期:  2021-10-21
  • 网络出版日期:  2022-05-12

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