张帆, 陈雷, 张士峰, 孙雷, 刘昆. 宇航用SRAM型FPGA的在线故障定位[J]. 微电子学与计算机, 2021, 38(12): 54-60. DOI: 10.19304/J.ISSN1000-7180.2021.0515
引用本文: 张帆, 陈雷, 张士峰, 孙雷, 刘昆. 宇航用SRAM型FPGA的在线故障定位[J]. 微电子学与计算机, 2021, 38(12): 54-60. DOI: 10.19304/J.ISSN1000-7180.2021.0515
ZHANG Fan, CHEN Lei, ZHANG Shifeng, SUN Lei, LIU Kun. Online fault diagnosis of SRAM-based FPGA in aerospace application[J]. Microelectronics & Computer, 2021, 38(12): 54-60. DOI: 10.19304/J.ISSN1000-7180.2021.0515
Citation: ZHANG Fan, CHEN Lei, ZHANG Shifeng, SUN Lei, LIU Kun. Online fault diagnosis of SRAM-based FPGA in aerospace application[J]. Microelectronics & Computer, 2021, 38(12): 54-60. DOI: 10.19304/J.ISSN1000-7180.2021.0515

宇航用SRAM型FPGA的在线故障定位

Online fault diagnosis of SRAM-based FPGA in aerospace application

  • 摘要: SRAM型FPGA的可重构能力已经被用于实现宇航应用FPGA的故障定位,通常故障定位采用覆盖性测试,需进行多次“码流加载、测试”的迭代.FPGA码流规模的增加,使得迭代测试消耗时间以及测试码流存储空间的不断提高,而这种需求几乎无法在空间电子系统中实现.本文通过码流解析,总结多组码流地址计算公式,包括待测单元坐标、行地址、主地址、辅地址等信息.借助码流地址计算公式可实现任意物理位置Tile(基本单元)的码流寻址并可确认Tile内部结构配置信息.在此基础上提出一种在待测FPGA本地进行分区对比测试的故障定位方法,可将FPGA资源分割为小的待测区域格,待测区域码流复制到相邻位置,并构建基于线性反馈移位寄存器的测试结构,逐格对比实现故障定位.最后,为了实现最高效率的故障定位,对故障定位的网格尺寸进行优化,以XC7VX330T为例,选择最优的网格尺寸后故障定位的时间小于619秒.与此前的故障定位技术相比, 此方法不需要提供额外的外部存储空间,能够降低电子系统在宇航应用中的载荷

     

    Abstract: The reconfigurability of SRAM-based FPGA has been used for fault diagnosis in aerospace applications. In general, fault diagnosis adopts coverage testing and multiple iterations of "bitstream loading and testing". The growing scale of FPGA's bitstream requires longer time on coverage testing and more storage space for bitstreams, which is hardly feasible in aerospace electronic systems. Analyzing bitstream and summarizing the relevant multi-group calculation formulas, including information such as cell coordinates, row addresses, major addresses, minor addresses, etc. which helps in diagnosing the bitstream of tile (the basic unit) and confirming the information of tiles' internal structure configurations. Based on the formulas, a method of fault diagnosis is proposed through comparison tests in FPGA undertest. This method divides FPGA's resources into small grids, copies the bitstream from area undertest to a adjacent location, organize testing structures based on linear feedback shift registers, and make comparisons grid by grid for fault diagnosis. Furthermore, this paper optimizes the grid size for fault diagnosis. The optimization demonstrated on XC7VX330T shows that the time of fault diagnosis is less than 619 seconds. Compared to existing fault diagnosis methods, external storage space is not required, which benefits electronic systems with reducing loads in aerospace applications.

     

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