姜云龙, 余隽, 刘俊良, 施展. 一种用于可穿戴医疗设备的低压超低功耗SAR ADC[J]. 微电子学与计算机, 2021, 38(12): 86-92. DOI: 10.19304/J.ISSN1000-7180.2021.0482
引用本文: 姜云龙, 余隽, 刘俊良, 施展. 一种用于可穿戴医疗设备的低压超低功耗SAR ADC[J]. 微电子学与计算机, 2021, 38(12): 86-92. DOI: 10.19304/J.ISSN1000-7180.2021.0482
JIANG Yunlong, YU Jun, LIU Junliang, SHI Zhan. A low voltage ultra low power SAR ADC for wearable medical devices[J]. Microelectronics & Computer, 2021, 38(12): 86-92. DOI: 10.19304/J.ISSN1000-7180.2021.0482
Citation: JIANG Yunlong, YU Jun, LIU Junliang, SHI Zhan. A low voltage ultra low power SAR ADC for wearable medical devices[J]. Microelectronics & Computer, 2021, 38(12): 86-92. DOI: 10.19304/J.ISSN1000-7180.2021.0482

一种用于可穿戴医疗设备的低压超低功耗SAR ADC

A low voltage ultra low power SAR ADC for wearable medical devices

  • 摘要: 针对可穿戴医疗设备,设计了一款0.5 V供电、2 kS/s采样率、10 bit精度的低压超低功耗逐次逼近型模数转换器(SAR ADC).设计采用自举采样开关来实现高线性采样.在低功耗策略上,使用了0.5 V的电压供电,使电路中绝大多数晶体管处于亚阈值区,由此产生的极低的电流对整体功耗的降低起了关键作用.另一种低功耗策略表现为在各个模块的选择、设计上,采用的5~5分段且逐位分裂的DAC电容阵列在降低自身能耗的同时省去了基准电路,降低了整体功耗,比较器以及SAR逻辑均采用无静态功耗的动态结构来降低能耗,此外,特别地提出了一种具有控制状态检测的高能效的控制电路,该电路不仅解决了由于时序处理不当而产生比较器误判的问题,且每个模块可以控制4个电容,提高控制效率的同时也降低了能耗.基于SMIC 0.18 μm CMOS工艺进行设计与后仿真,仿真结果表明,在0.5 V供电、2 kS/s采样率下,电路可达到的有效位数(ENOB)为9.68 bit,信噪失真比(SNDR)为60.1 dB,功耗为15.45 nW,品质因数(FOM)为9.4 fJ/conv-step.

     

    Abstract: A low-voltage ultra-low power SAR ADC with 0.5 V power supply, 2 kS/s sampling rate and 10 bit accuracy is designed for wearable medical devices. The design uses bootstrap sampling switch to achieve high linear sampling. In the low-power strategy, a voltage of 0.5 V is used to supply power, so that most of the transistors in the circuit are in the sub threshold region. The resulting extremely low current plays a key role in reducing the overall power consumption. Another low-power strategy is that in the selection and design of each module, the 5~5 segmented and bit by bit split DAC capacitor array is used to reduce its own energy consumption while omitting the reference circuit and reducing the overall power consumption. The comparator and SAR logic adopt the dynamic structure without static power consumption to reduce the energy consumption. In addition, an energy-efficient control circuit with control state detection is proposed. The circuit not only solves the problem of comparator misjudgment due to improper timing processing, but also can control four capacitors per module, which improves the control efficiency and reduces the energy consumption. Based on SMIC 0.18 μm CMOS process, the design and post simulation results show that under 0.5 V power supply and 2 kS/s sampling rate, the circuit can achieve ENOB of 9.68 bit, SNDR of 60.1 dB, power consumption of 15.45 nW and FOM of 9.4 fJ/conv-step.

     

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