Abstract:
To enhance the throughput of Physical Downlink control channel (PDCCH)Polar decoded and to reduce the complexity of the 5th wireless communication terminal equipment, this paper proposes a Polar decoder algorithm suitable for semiconductor chip design. In view of the characteristics of PDCCH, the decoding of PDCCH Polar is studied by using the method of CRC-Aided successive cancellation method. Polar decoding complexity was simplified by optimizing the path selection through path sorting and distributed CRC early stop function. And the throughput is enhanced by using the method of paralleled processing for chip design. Simulation results show that this method not only reduces the complexity, but also guarantees the decoding performance.