一种900 V JTE结构VDMOS终端设计
Design of 900 V JTE Structure VDMOS Termination
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摘要: 垂直双扩散金属氧化物场效应晶体管(Vertical Double-diffused Metal-Oxide-Semiconductor Field Transistor, VDMOS)是由Pbody与外延层之间形成的PN结承受电压, 由于工艺限制, 元胞区域只能设计为突变结, 而终端区域最常用的结构为场限环, 在原理上也相当于突变结耐压.结合结终端扩展(Junction Termination Extension, JTE)技术, 引入缓变结耐压, 设计了一款900 V的终端结构, 实现了992.0 V的仿真击穿电压, 终端效率达到了98.6%, 而且有效终端长度仅有130.2 μm, 在较大程度上减小了芯片的占用面积, 提高了击穿电压, 而且工艺流程与成熟的深阱场限环基本一致, 有较好的兼容性.Abstract: The breakdown voltage of Vertical Double-diffused Metal-Oxide-Semiconductor Field Transistor(VDMOS) is withstood by the PN junction form by Pbody and EPI. The cell region is designed as a abrupt junction because of the technique limitation.Field Limit Ring(FLR) is the most common structure used in termination region, and it can also take as a abrupt junction. In this paper, a 900 V termination structure is designed with the introduction of graded junction and the combination of Junction Termination Extension(JTE). The simulation breakdown voltage 992.0V with the effective termination length of only 130.2 μm, and the efficiency is 98.6%. The chip area is significantly decreased, breakdown voltage is significantly increased, and the technique is the same to deep well FLR's, which means a good technique compatibility.
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