基于热影响及布局利用率的三维集成电路布局规划算法设计
Design of Floorplanning Algorithm in Three-Dimension Integrated Circuit Based on Thermal and Utilization
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摘要: 针对三维集成电路设计流程中存在的布局规划问题, 提出了协同考虑热影响和布局利用率的布局规划算法设计方案, 并利用多次模拟退火过程, 实现完整三维集成电路布局规划算法的设计流程.通过对通用的MCNC benchmark基准电路的验证, 相比已有的布局规划方案, 该布局规划算法在峰值温度降低3%左右的情况下, 在布局利用率上能够得到平均30%以上的性能提升.Abstract: To address the floorplanning problem in 3D IC design flow, this paper proposes a floorplanning algorithm based on thermal and utilization. Several simulated annealing processes are also used in the design. At last, a modified 3D IC floorplanning design flow is completed. This paper verifies the new algorithm on MCNC benchmark circuits. According to the result, the new algorithm improves the floorplanning utilization above 30% in average as well as decreases peak temperature by about 3%.
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