A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging
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摘要:
拓展摩尔定律已成为集成电路及电子信息通信硬件产业的重大战略之一, 其中微系统技术发展进入全新阶段, 集成电路芯片与集成封装组件的界限日渐模糊, 形成了融合发展的新局面, 正对微系统异质集成技术领域发展产生深远影响.结合团队科研实践, 本文从架构演进、芯片-封装一体化设计策略、多物理域协同分析与优化、集成平台的重大创新等层面, 分析IC与集成封装融合发展阶段的技术特征、内涵与动向, 并对未来应用前景、发展路径进行展望.
Abstract:"More than Moore" has become the preferred strategy for integrated circuit and electronic, information and telecommunication hardware industries and therefore has just promoted microsystem technology onto a new stage, whereon the boundary between IC (integrated circuit) chips and system-level electronic package has become increasingly blurred, triggering a fashion of integrated development of two domain. This new stage is now exerting a far-reaching influence on the development of microsystem heterogeneous integration domain. Consequently, based on the personal scientific research practice, the characteristics, connotations and trends are analyzed and inferred in-depth for this whole new IC-package co-development stage, from the perspective of architecture evolution, chip-package co-design strategy, multi-physics co-analysis and co-optimization, and major technical innovations in integrated assembling and manufacturing; in addition, the future applications are prospected and the path of evolution is suggested.
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图 4 Grenoble Alpes大学、CEA-LIST及Mentor、STM等产学研机构联手在有源转接板上实现的芯粒集成[10]
图 5 芯片/系统封装/电路板协同设计[3]
图 8 多物理场/多尺度联合仿真设计的关注重点[3]
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[1] WALDROP M M. The chips are down for Moore's law[J]. Nature, 2016, 530(7589): 144-147. DOI: 10.1038/530144a. [2] International Roadmap for Devices and Systems. International roadmap for devices and systems (IRDS?) 2020 edition[EB/OL]. IEEE, 2020[2020-10-11]. https://irds.ieee.org/editions/2020. [3] Heterogeneous integration roadmap: 2019 Edition[EB/OL]. IEEE, 2019. [2020-10-11] https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html. [4] WU T T, SHEN C H, SHIEH J M, et al. Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for internet of things[C]//2015 IEEE International Electron Devices Meeting (IEDM). Washington, DC, USA: IEEE, 2015: 640-643. [5] COUDRAIN P, CHARBONNIER J, GARNIER A, et al. Active interposer technology for chiplet-based advanced 3D system architectures[C]//2019 69th Electronic Components and Technology Conference (ECTC). Las Vegas, NV, USA, USA: IEEE, 2019: 568-578. [6] 许居衍.复归于道--封装改道芯片业(演讲记录稿)[J].电子与封装, 2019, 19(10): 1-3. DOI: 10.16257/j.cnki.1681-1070.2019.1001.XU J Y.Back to the Origin-Packaging are Changing the Path of IC Industry: a Transcript for the Keynote Speech[J]. Electronics & Packaging, 2019, 19(10): 1-3. DOI: 10.16257/j.cnki.1681-1070.2019.1001. [7] BECK N, WHITE S, PARASCHOU M, et al. 'Zeppelin': An SoC for multichip architectures[C]//2018 IEEE International Solid-State Circuits Conference-(ISSCC). San Francisco, CA, USA: IEEE, 2018: 40-42. [8] LIN M S, HUANG T C, TSAI C C, et al. A 7nm 4GHz Arm-core-based CoWoS chiplet design for high performance computing[C]//2019 Symposium on VLSI Circuits. Kyoto, Japan: IEEE, 2019: C28-C29. [9] GREENHILL D, HO R, LEWIS D, et al. 3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration[C]//2017 IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2017: 54-55. [10] VIVET P, GUTHMULLER E, THONNART Y, et al. A 220GOPS 96-core processor with 6 chiplets 3D-stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-chiplet interconnects and 156mW/mm2@ 82%-Peak-efficiency DC-DC converters[C]//2020 IEEE International Solid-State Circuits Conference-(ISSCC). San Francisco, CA, USA, USA: IEEE, 2020: 46-47. [11] MA S L, CHAI Y, YAN J, et al. A 2.5D integrated L band Receiver based on High resistivity Si interposer[C]//2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). Beijing, China: IEEE, 2018: 74-77. [12] PARES G, JEAN-PHILIPPE M, EDOUARD D, et al. Highly compact RF transceiver module using high resistive silicon interposer with embedded inductors and heterogeneous dies integration[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). Las Vegas, NV, USA, USA: IEEE, 2019: 1279-1286. [13] CHROSTOWSKI L, HOCHBERG M. Silicon photonics design: from devices to systems[M]. Cambridge: Cambridge University Press, 2015. [14] 解决高密度先进封装的设计与验证挑战[EB/OL]. [2020-10-11]. https://www.mentor.com/pcb/resources/overview/solving-the-design-and-verification-challenges-of-high-density-advanced-packaging-bc555a84-e9be-42c5-990b-dba9b4391c0c. -