Abstract: In this paper, We research LOD and WPE effects of self-developed 40nm process PDK.The parameter SA of LOD effect and the parameter left of WPE effect influence the characteristics of CMOS device, especially the saturation current I_dsat and the threshold voltage V_TH. With the decrease of SA, I_dsat of NMOS decreases by 4.25% and V_TH increases by 2.79%.The relationship between electrical parameters and SA of PMOS is consistent with that of NMOS, but the trend is stronger than NMOS, I_dsat decreases by 8.32% and V_TH increases by 6.78%. The physical mechanism of LOD effect is explained.With the decrease of left, the I_dsat of NMOS decreases by 9.03% and V_TH increases by 12.5%.The relationship between the electrical parameters of PMOS and left is weaker than that of NMOS, I_dsat decreases by 8.50%, and V_TH increases by 4.61%.The cause that the electrical parameters change under WPE effect is proposed. In the nanometer process PDK, the accurate application of LOD and WPE effects can better simulate device performance, and improve the precision of circuit.