Design of RISC-V processor based on Chisel
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摘要:
近年来，RISC-V在处理器领域的大行其道，不仅仅在于其开源可扩展的指令集架构属性，同时也得益于加州大学伯克利分校为其量身打造的敏捷化设计语言Chisel，极大降低了处理器设计门槛.本文基于Chisel语言设计实现了一款带有扩展指令协处理器的多核RISC-V芯片，相对于传统的硬件设计语言，将硬件IP的设计与集成周期压缩50%以上，并且依靠丰富的模板资源，能够快速完成拓扑互连、时序分割、跨时钟域转换等影响处理器整体性能的全局性优化设计，将芯片验证与实现的迭代周期缩短30%以上，为开源处理器敏捷化开发探索了行之有效的技术手段.
Abstract:In recently years, RISC-V′s popularity in the field of processors is not only due to its open-source and extensible instruction set architecture attributes, but also thanks to Chisel, an agile design language tailored by UC Berkeley, greatly reducing the threshold of processor design.A multi-core RISC-V chip with extended instruction coprocessor based on Chiselis designed and implemented in this paper. Compared with the traditional hardware design language, the design and integration time of hardware IP is compressed by more than 50%. At the same time, relying on rich template resources, it can quickly complete the global optimization design that affects the overall performance of the processor, such as topology interconnection, timing segmentation, and cross-clock domain conversion, reducing the iteration time of chip verification and implementation by more than 30%. The open-source processor agile development has explored effective technical means.
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